Semiconductor manufacturing companies, such as TSMC, generally provide a comprehensive portfolio/library of foundry proven silicon designs, such as cells, arrays, blocks, etc. to their customers for use as design building blocks for customer devices. The customer uses the provided library of building blocks to design the layout, shape, interconnection, and configuration of a proposed device. Once the design for the proposed device is completed by the customer, the design is forwarded to the semiconductor manufacturing company for the final stage of the design process (tape out) prior to manufacturing the proposed device.
However, the manufacturing process, which includes the initial tooling up for the proposed device at the foundry, is generally the most costly part of a proposed device's design. Therefore, the semiconductor manufacturing company generally conducts several tests on the proposed device design prior to proceeding with the tape out process. One example of pre-tape out testing is design rule checking (DRC), which generally includes determining whether the proposed device design satisfies a series of recommended parameters called design rules. Design rules are a series of manufacturing process specific parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a schematic and/or mask set. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, to ensure that the device will operate properly once manufactured. Design rule checking is a major step during physical verification process for the proposed device design, and also generally includes layout verses schematic (LVS) checking, XOR checks, electrical rule checking (ERC), and Antenna Checks. These checks are designed to achieve an overall high yield and reliability in the proposed device once manufactured.
The semiconductor manufacturing companies may insert an intellectual property (IP) tag into each design, where each IP has a tag may identify vendor, product, and/or version information. Foundries may obtain IP information by scanning those IP tags from the customer or design house layouts to verify the IP correctness of the design in the layout, and to make sure that a customer has not moved the cells or changed the CAD layers from the IP in a manner that will cause functional problems in the circuit. However, foundries often times have problems scanning for IP, especially in the SRAM art. Generally, when a cell is tagged or marked to identify IP in the cell, the IP tag is on the top cell of the layout, however, when a design house uses IP in a product, such as an SRAM, they may reduplicate sub-cells for extending the SRAM size, which makes it difficult for the foundry to scan for IP tags. For example, a foundry may make available a 256 KB SRAM layout to design houses, and the design house may duplicate the IP from the layout multiple times and put the duplicated units together to build a 64 MB SRAM. In this situation, the top cell of the given IP will not be included in the 64 MB SRAM, and as such, the foundry cannot get any IP information from scanning the 64 MB SRAM layout.
In situations where the customer or design house has modified the layout in a manner that makes the IP tags unreadable, the cell layout verification must be conducted manually. For example, in situations where foundries have problems scanning for IP tags, the foundries must locate the cells containing the foundry IP manually from CAD layers, which covers all of the layout area. Once the cells containing the IP are found, they must then be manually compared to the cells of the original IP, which is a time consuming and inaccurate task. Therefore, it would be desirable to have a system, method, or software package that enhances cell recognition and verification of IC design.